Low-capacitance bonding pad for semiconductor device

ABSTRACT

A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of, and claims the prioritybenefit of, U.S. application Ser. No. 09/329,648 filed on Jun. 9, 1999.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device. Moreparticularly, the present invention relates to a bonding pad with lowcapacitance for a semiconductor device.

2. Description of the Related Art

Trends for electrical products are light, short, small, and thin.Usually, the chips manufacturing technology and the packaging technologyare rapidly developed to meet these trends. However, due to a limitationof bonding machines, a size of a bonding pad for a semiconductor deviceis not reduced as well as a line width of a chip is greatly reduced.Because the size of the bonding pad is insufficiently small, an area ofa substrate overlapped by the bonding pad is large. As a result, aparasitic capacitance of the bonding pad remains high. Additionally, apeel-off effect often occurs while forming the bonding wire, so thatbonding reliability is decreased.

FIG. 1 is a cross-sectional view, schematically illustrating aconventional bonding pad.

Referring to FIG. 1, a dielectric layer 12 is formed on a substrate 10,and a metal layer 14 is formed on the dielectric layer 12. A passivationlayer 16 having a bonding pad opening 18 is formed on the metal layer14. A bonding pad wire 19 is formed on the metal layer 14 within thebonding pad opening 18. A parasitic capacitance of the bonding pad maybesmall if the distance between the substrate 10 and the metal layer 14 islarge. But if the bonding pad is only formed by the uppermost metallayer to increase the distance between the substrate 10 and the metallayer 14, the peel-off effect, denoted as a region 17, often occursduring formation of the bonding wire 19 and chip packaging. The bondingreliability is therefore reduced due to the peel-off effect.

SUMMARY OF THE INVENTION

The present invention provides a low-capacitance bonding pad for asemiconductor device so as to avoid a peel-off effect and reduce aparasitic capacitance of the bonding pad.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a low-capacitance bonding pad for a semiconductordevice. A diffusion region is formed in a substrate at a region on whicha bonding pad is to be formed. The bonding pad includes a stacked metallayer and a metal layer, in which the metal layer is on the stackedmetal layer. The stacked metal layer includes several metal layers andseveral dielectric layers, in which the metal layers are isolated by thedielectric layers in between by alternately stacking them up. The metallayers stacked in the stacked metal layer are formed with small areas.Each of the metal layers stacked in the stacked metal layer is coupledwith an adjacent metal layer by a via plug.

Since the bonding pad includes several metal layers and buried deeply inthe dielectric layer, the peel-off effect is effectively avoided. Anarea of the substrate overlapped by the metal layers stacked in thestacked metal layer is small because the areas of the metal layersstacked in the stacked metal layer are small. As a result, the parasiticcapacitance of the bonding pad is also effectively reduced. Moreover,the parasitic capacitance of the bonding pad is further reduced due tothe diffusion region in the substrate, which serves as an additionalcapacitor coupled in series to the capacitor induced by the metallayers. The metal layers in the stacked metal layer can include variousgeometry structures. For example, the metal layer includes several metalbars in one layer and crosses to each other in different layer indifferent bar direction so as to form a geometric structure, such as anet structure or any other overlapping structure.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides another low-capacitance bonding pad for asemiconductor device. A device is formed under a bonding pad which ismade from a stacked metal layer and an uppermost metal layer. The metallayers stacked in the stacked metal layer are formed with small area andeach area of the metal layer in the stacked metal layer is smaller thanthe uppermost metal layer.

The device is formed on a substrate. Several metal layers close to thedevice serve as signal lines. Several metal layers stacked on the metallayers as signal lines serve as power lines, and other metal layersstacked on the power lines serve as the bonding pad which consists of astacked metal layer and an uppermost metal layer. The metal layers inthe stacked metal layer can include various geometry structures. Forexample, the metal layer includes several metal bars in one layer andcrosses to each other in different layer in different bar direction soas to form a geometric structure, such as a net structure or any otheroverlapping structure.

Because the device is formed between the bonding pad and the substrate,an area of the integrated circuits layout is reduced. The area of thesubstrate overlapped by the metal layers stacked in the stacked metallayer is small since areas of the metal layers are small, so that theparasitic capacitance of the bonding pad is reduced. The peel-off effectis avoided and the bonding reliability increases because the bonding padincludes the stacked metal layers which are buried deeply in thedielectric layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention. In the drawings,

FIG. 1 is a schematic drawing, illustrating a cross-sectional view of aconventional bonding pad;

FIG. 2 is a schematic drawing, illustrating a top view of a bonding padlayout according to the invention;

FIG. 3 is a schematic drawing, illustrating a cross-sectional view ofFIG. 2 taken along a line III—III;

FIG. 4 is a schematic drawing, illustrating a cross-sectional view ofFIG. 2 taken along a line IV—IV;

FIG. 5 is a schematic drawing, illustrating a cross-sectional view ofFIG. 2 taken along a line V—V;

FIG. 6 is a schematic drawing, illustrating a cross-sectional view ofFIG. 2 taken along a line VI—VI;

FIG. 7 is another schematic drawing, illustrating a top view of abonding pad layout according to the invention;

FIG. 8 is a schematic drawing, illustrating a cross-sectional view ofFIG. 7 taken along a line VIII—VIII;

FIG. 9 is another schematic drawing, illustrating a top view of abonding pad layout according to the invention;

FIG. 10 is a schematic drawing, illustrating a cross-sectional view ofFIG. 9 taken along a line X—X;

FIG. 11 is another schematic drawing, illustrating a top view of abonding pad layout according to the invention;

FIG. 12 is a schematic drawing, illustrating a cross-sectional view ofFIG. 11 taken along a line XII—XII;

FIGS. 13 through 16 are schematic drawings, illustrating cross-sectionalviews of bonding pad layouts according to the invention;

FIGS. 17 through 22 are schematic drawings, illustrating cross-sectionalviews of bonding pad layouts according to the invention; and

FIG. 23 is a schematic drawing, illustrating a cross-sectional view ofanother bonding pad layout according to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

EXAMPLE 1

FIG. 2 is a schematic drawing, illustrating a top view of a bonding padlayout according to the invention. FIGS. 3, 4, 5 and 6 are schematicdrawings, illustrating cross-sectional views of FIG. 2 taken along linesIII—III, IV—IV, V—V and VI—VI, respectively.

Referring to FIGS. 2 and 4, a p-type substrate 200 having an n-well 202is provided. A p-type doped region 204 is formed as a diffusion regionin the n-well 202. A bonding pad includes a stacked metal layer 208 anda metal layer 250 lies located on the p-type substrate 200 and isaligned with the p-type doped region 204. The stacked metal layer 208includes several metal layers 210, 220, 230, 240 and several dielectriclayers 212, 222, 232, 242, 252. Additionally, the metal layers 210, 220,230, 240 and the dielectric layers 212, 222, 232, 242, 252 are stackedalternately on the p-type substrate 200. The metal layer 250 is formedon the dielectric layer 252. In this structure as described above, ajunction capacitance C_(P) occurs between the n-well 202 and the p-typedoped region 204. A junction capacitance C_(N) occurs between the n-well202 and the p-type substrate 200. A total equivalent capacitance C_(Meq)also occurs due to contribution from the metal layers 210, 220, 230,240, 250. All the capacitance of C_(P), C_(N), and C_(Meq) are coupledin series so that a parasitic capacitance of the bonding pad iseffectively reduced.

The metal layers 210, 220, 230, and 240 are all designed, for example,to have a bar structures in this embodiment but the metal layer 250 is aplanar layer. Each width of the metal layers 210, 220, 230 and 240 isdesigned to be as small as possible, so that an area of the p-typesubstrate 200 overlapped by the metal layers 210, 220, 230 and 240 isreduced. This is significantly helpful to reduce the parasiticcapacitance of the bonding pad.

The metal layers 210 and 240 are parallel to a row direction 400 shownin FIG. 2, and the metal layer 240 is aligned with the metal layer 210.Additionally, the metal layers 220 and 230 are parallel to a columndirection 300 shown in FIG. 2 and perpendicular to the row direction400. Similarly, the metal layer 230 is aligned with the metal layer 220.As a result, the metal layers 210 and 240 are shown as a layer structurein FIG. 4 but not shown in FIG. 3 due to the different cross-sectionalline III—III. In FIGS. 5 and 6, the metal layers 210 and 240 are shownlike bars which are not connected to each other, and the metal layer 210is aligned with the metal layer 240. Similarly, the metal layers 220 and230 are shown as bars in FIG. 6 and not shown in FIG. 5. In FIGS. 3 and4, the metal layers 220 and 230 are shown as bars that are not connectedto each other, and the metal layer 230 is aligned with the metal layer220. A layout of the metal layers 210, 220, 230 and 240 resembles a meshor a net as shown in FIG. 2.

In the invention, each of the metal layers 210, 220, 230, 240 and 250are connected with the adjacent metal layers by via plugs 214, 224, 234,244 in the dielectric layers 222, 232, 242, and 252. In order to avoidthe peel-off effect, the via plugs are alternately positioned in theadjacent dielectric layers 222, 232, 242, and 252 so as to achieve auniform distribution of the via plugs 214, 224, 234, 244. For example,the via plug 244 is not aligned with the via plug 234 as shown in FIG.4. Similarly, the via plug 234 and the via plug 224 are not aligned andthe via plug 224 and the via plug 214 are also not aligned as shown inFIG. 2. This structure can effectively avoid the peel-off effect due toa uniform stress. The via plug 224 connecting the metal layers 220 and230 is only shown in FIGS. 3 and 6. The via plug 214 connecting themetal layers 210 and 220 and the via plug 234 connecting the metallayers 230 and 240 are only shown in FIGS. 4 and 6 due to differentcross-sectional views. The via plug 244 connecting the metal layers 240and 250 is only shown in FIGS. 4 and 5. Furthermore, the via plug 214 isaligned with the via plug 234 and is not aligned with the via plugs 224and 244, as shown in FIGS. 4 and 6.

A passivation layer 262 is formed on the metal layer 250 with a bondingpad opening 270 used for a subsequent bonding process.

The bonding pad according to the invention includes the stacked metallayer 208 and the metal layer 250. The peel-off effect is effectivelyavoided by this structure. The area of the p-type substrate 200overlapped by the metal layers 210, 220, 230 and 240 is decreased byabout 50% comparing with the conventional bonding pad. Because of thediffusion region, that is, the p-type doped region 204 in the invention,the junction capacitance C_(P) between the n-well 202 and the p-typedoped region 204, the junction capacitance C_(N) between the n-well 202and the p-type substrate 200 and the total equivalent capacitanceC_(Meq) between the substrate 200 and the metal layers 210, 220, 230,240, 250 are series connected. As a result, the parasitic capacitance ofthe bonding pad is about 50% less than that of the conventional bondingpad.

A layout of the metal layers 210, 220, 230 and 240 mentioned above isnot the only way to reduce the area of the p-type substrate 200overlapped by the metal layers 210, 220, 230 and 240 according to theinvention.

FIG. 7 is a top view of a portion of a substrate, schematicallyillustrating a bonding pad layout according to the invention, and FIG. 8is a cross-sectional view, schematically illustrating the bonding padtaken along a line VIII—VIII of FIG. 7. In FIGS. 7 and 8, the metallayers are referred in numerals 710, 720, 730, 740 and 750. Each of themetal layers 710, 720, 730 and 740 are designed as a bar, and the metallayer 750 is a planar layer. The metal layers 710, 720, 730 and 740 arealigned with each other and are isolated by several dielectric layers212, 222, 232, 242 in between. A top dielectric layer 252 covers themetal layer 740. The metal layer 750 is located on the dielectric layer252. Additionally, a direction of the metal layers 710, 720, 730 and 740deviates from the direction 400 (FIG. 2) with an angle, which preferablyis 45 degrees in this embodiment.

Referring to FIGS. 7 and 8, each of the metal layers 710, 720, 730, 740and 750 are coupled with the adjacent metal layers by via plugs 714,724, 734, 744 in the dielectric layers 212, 222, 232, 242. Positions ofthe via plugs are not aligned for two adjacent layers. In this manner,the via plug 714 and the via plug 724 are not aligned, the via plug 724and the via plug 734 are not aligned, and also the via plug 734 and thevia plug 744 are not aligned. The via plug 714 and the via plug 734 maybe aligned and the via plug 724 and the via plug 744 may be aligned. Asa result, the position of the via plug 724 connecting the metal layers720 and 730 is not superimposed on the position of the via plug 714 usedto connect the metal layers 710 and 720 as shown in FIG. 8. The positionof the via plug 734 connecting the metal layers 730 and 740 is notsuperimposed on the position of the via plug 724. However, the via plug734 is aligned with the via plug 714, and the via plug 744 is alignedwith the via plug 724.

Based on a concept of reducing the area of the substrate overlapped bythe metal layers, other layouts of the metal layers are also suitablefor the invention.

FIGS. 9 and 11 are top views of a portion of a substrate, schematicallyillustrating another two bonding pad layouts according to the invention,and FIGS. 10 and 12 are cross-sectional views, schematicallyillustrating the bonding pad layouts respectively taken along lines X—Xand XII—XII in FIG. 9 and FIG. 10. A layout of the metal layers in FIG.9 includes, for example, several concentric circles, and a layout of themetal layers in FIG. 11 is concentric polygons, such as squares.

In FIGS. 9 and 10, the metal layers are referred in numerals 910, 920,930, 940 and 950. Each of the metal layers 910, 920, 930 and 940 aredesigned as concentric circles, and the metal layer 950 is a planarlayer. Referring to FIGS. 9 and 10, the metal layers 910, 920, 930 and940 are aligned with each other, and each of the metal layers 910, 920,930, 940, 950 are coupled by via plugs 914, 924, 934, 944, which areformed in several isolation layers, such as the dielectric layers 212,222, 232, 242, 252 as shown in the previous examples. Again, the viaplugs 914, 924, 934, 944 are alternately distributed for the twoadjacent layers. The design concept of this layout is the same as theprevious designs.

In FIGS. 11 and 12, the metal layers are referred to by numerals 1110,1120, 1130, 1140 and 1150. The metal layers 1110, 1120, 1130 and 1140are designed as concentric squares, and the metal layer 1150 is a plane.Referring to FIGS. 11 and 12, the metal layers 1110, 1120, 1130 and 1140are aligned with each other, and each of the metal layers 1110, 1120,1130, 1140 and 1150 are coupled with the adjacent metal layers by viaplugs 1114, 1124, 1134 and 1144. The design concept of this layout isthe same as the previous designs.

FIGS. 13, 14, 15 and 16 are top views of a portion of a substrate,schematically illustrating other bonding pad layouts for the metallayers 210, 220, 230 and 240 according to the invention. Layouts of themetal layers in FIGS. 13, 14, 15 and 16 respectively are concentricpentagons, concentric hexagons, concentric heptagons and concentricoctagons. The design concept of these layouts is the same as theprevious examples. According to the concept, other kinds of polygons arealso acceptable in the invention.

In FIGS. 17 and 18, the layouts of the metal layers 210, 220, 230 and240 resemble meshes. The layout shown in FIG. 17 is a honeycombed typemesh, and the layout shown in FIG. 18 is a mesh composed of adjacentoctagonal units arranged in rows. The mesh in the invention comprises amesh composed of a unit shape as seen in FIGS. 17 and 18. However, amesh composed of various unit shapes is suitable for the invention. InFIG. 19, the layout of the metal layers 210, 220, 230 and 240 is a meshcomposed of rows of pentagonal structures connected by a line, with eachpentagonal unit connected to the pentagon in the row above or below by aline. Each unit shape of the mesh is changed to a heptagon, an octagonand a circle in FIGS. 20, 21 and 22, respectively. Also, other kinds ofpolygons are acceptable.

Although only a few layouts for the metal layers are disclosed in theembodiment. An implementation of the layout is not limited by thedisclosed examples because the concept disclosed in the invention is toreduce the area of the substrate overlapped by the metal layers. By thisconcept, the parasitic capacitance of the bonding pad is reduced and thepeel-off effect is avoided. As a result, any kind of layout that meetsthe concept is suitable for the invention. The bonding pad layout can bedesigned with many types of unit shape that meet the concept, so thatany kind of geometry is suitable for use in the invention.

EXAMPLE 2

In a conventional semiconductor device, the bonding pad is not formedabove an active device region or circuit region because a subsequentbonding wire process could damage the formed device.

This issue can also be solved by the invention. Since the bonding pad ofthe invention include a top metal layer 250 of FIG. 4 and the stackedmetal layer 208. The bonding pad opening 270 can be adjusted at thelocation above the device region. As a result, the available substratesurface can be more efficiently used.

FIG. 23 is a cross-sectional view, schematically illustrating a bondingpad layout with a device, according to the invention. In this example 2,devices are formed on the substrate just under the bonding pad.

Referring to FIG. 23, a device 32, such as a field effect transistor, isformed on a substrate 30. Metal layers 51, 52, 53, 54, 55 and 56 areformed in a dielectric layer 60 over the device 32, in which thedielectric layer 60 serves as an isolation and a frame to stack themetal layers 51, 52, 53, 54, 55, 56. The dielectric layer 60 can alsofurther include several sub-layers to hold and isolate the metal layers.A bonding pad includes the metal layers 55 and 56 and is covered by thea passivation layer 80. The passivation layer 80 includes a bonding padopening 82, which exposes a portion of the metal layer 56. The metallayers 51 and 52 near the substrate 30 are used to serve as, forexample, signal lines, and the metal layers 53 and 54 are designed to beplanar layers and used to serve as, for example, power lines. Apassivation layer 80 is formed on a dielectric layer 60, and the bondingpad opening 82 is formed in the passivation layer 80 to expose the metallayer 56. A bonding wire 84 is attached to the metal layer 56 within thebonding pad opening 84. Each pair of the metal layers 51, 52, 53, 54, 55and 56 is isolated by the dielectric layer 60. The metal layers 55, 56are coupled by a via plug 75 and the metal layers 51, 52 are coupled bya via plug 71. The metal layers 52, 53 and 54 serving as signal linesand power lines are also coupled by via plugs (not shown), and the metallayers 54 and 55 are similar. However, these via plugs should not beformed under the bonding pad opening 82. Thus, the metal layers 53, 54can be used to be the buffer layers, and the bonding stress borne on theactive devices can be reduced through these buffer layers.

In the invention, the device 32, such as a CMOS device, is formed on thesubstrate 30 or an n-well 34 in the substrate 30. The metal layer 56 isa plane, and the metal layer 55 is designed as applying one of thelayouts shown in example 1 for the metal layer 55 so that the parasiticcapacitance and the bonding reliability of the bonding pad areeffectively reduced and increased, respectively.

According to the foregoing, the advantages of the invention include thefollowing:

1. The bonding pad in the invention is formed by multiple metal layersand buried deeply in the dielectric layer, so that the peel-off effectis avoided and the bonding reliability effectively increases.

2. In the invention, the overlapping area of between the substrate andthe metal layers is greatly reduced. The parasitic capacitance of thebonding pad is reduced.

3. A diffusion region is formed in the substrate so that the contactcapacitance of the diffusion region and the capacitance of the bondingpad are connected in series. The parasitic capacitance of the bondingpad is reduced.

4. The invention is compatible with the current conventional processes.Only the layout design of the bonding pad is changed to meet therequirement of a semiconductor device. Manufactures can achieve thebonding pad structure of the invention without modifying theirfabrication processes.

5. The device can be formed under the bonding pad so that the substratesurface is more efficiently used for compact circuit layout.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

What is claimed is:
 1. A low capacitance bonding pad structure for asemiconductor device, comprising: a substrate having a well; a dopedregion formed in the well as a diffusion region; a stack of metal layersalternating with dielectric layers on the doped diffusion region,wherein the metal layers are coupled with one and other by a pluralityof via plugs in the dielectric layers; an uppermost metal layerpositioned on the stack and aligned with the doped diffusion region,wherein the metal layers in the stack are arranged in a mesharrangement, distributed substantially evenly underneath the uppermostmetal layer, and an area of each metal layer in the stack is smallerthan that of the uppermost metal layer; and a passivation layer having abonding pad opening on the uppermost metal layer for externally electricconnection.
 2. The low-capacitance bonding pad of claim 1, wherein thetype of the ions doped in the doped region is opposite to those in thewell.
 3. The low-capacitance bonding pad of claim 1, wherein the metallayers in the stack are aligned with each other.
 4. The low-capacitancebonding pad of claim 1, wherein the mesh comprises a unit geometricshape.
 5. The low-capacitance bonding pad of claim 1, wherein the unitgeometric shape is a hollow polygon shape.
 6. The low-capacitancebonding pad of claim 1, wherein the unit geometric shape is a hollowcircle shape.